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    • 专利摘要:
    PURPOSE: A device control system is provided to control devices on a CPU board by using a SBEM(Serial Bus Extendable Module) in a case that a CPU controller can not be installed at the board so that it can easily extend the device control. CONSTITUTION: The system comprises an external board(50) and a CPU board(30). The CPU board(30) generates control signals for controlling plural electronic devices(X1-Xn). The CPU board(30) includes a CPU(31) and an SBEMC(Serial Bus Extendable Module to CPU, 33). The CPU(31) generates parallel control signals for controlling the devices(X1-Xn) of the external board(50), and the SBEMC(33) converts the parallel control signals into the serial control signals. An SBEMD(Serial Bus Extendable Module to Device chip, 35) of the external board(50) receives the serial control signals with clock signals and frame signals from the SBEMC(33). The SBEMC(33) and the SBEMD(35) are made of FPGAs(Field Programmable Gate Arrays) or PLDs(Programmable Logic Devices) for converting parallel signals into serial ones, and addressing each serial control signal.
    公开号:KR20030035079A
    申请号:KR1020010066956
    申请日:2001-10-30
    公开日:2003-05-09
    发明作者:강인용
    申请人:엘지전자 주식회사；
    IPC主号:
    专利说明:

    Device Control System {DEVICE CONTROL SYSTEM}
    [11] The present invention relates to a control system, and more specifically, to arrange a hardware bus extender module (SBEM) that can apply a control signal to device chips instead of a CPU controller and a communication controller to simplify the hardware configuration of the board and to easily control the device. It is about a device control system that can be extended.
    [12] 1 is a block diagram illustrating a device control system according to the prior art.
    [13] As shown in FIG. 1, the CPU board 10 includes a CPU unit 1 generating a parallel control signal for controlling the device chips 11 and 12 disposed on the external board 20, and the parallel control signal. Is converted into a serial control signal, and then transmitted to the external board (20).
    [14] In addition, the external board 20 receives a serial control signal transmitted from the communication controller 3 and converts it back into a parallel control signal and a parallel control signal from the communication controller 5. It is composed of a microcontroller (7) and a plurality of device chips (11, 12) connected to the microcontroller 7 to be applied and converted into a serial control signal, and then transmitted to the respective device chips (11, 12). .
    [15] This structured device control system operates as follows.
    [16] First, a parallel control signal is generated by the CPU 1 in the CPU board 10 to control a plurality of devices 11 and 12 disposed on the external board 20. The generated parallel control signal is converted into a serial control signal by the communication controller 3 and transmitted to the communication controller 5 in the external board 20. The communication controller 5 of the external board 20, which receives the serial control signal, converts it into a parallel control signal and transmits it to the microcontroller 7 again. The microcontroller 7 analyzes the parallel control signals to select which signals are the control signals of the respective device chips 11 and 12, and apply the same to control the signals.
    [17] However, the control system having the above structure requires not only a communication controller for both the CPU embedded board and the device chip embedded board, but also additionally needs to place a microcontroller on the device chip board in order to properly transmit control signals to the device chips. Therefore, the system configuration is complicated, and manufacturing costs are expensive.
    [18] In addition, since the microcontroller disposed on the external board has a limitation in scalability, it is difficult to transmit a control signal to multiple device chips.
    [19] In other words, as control device chips increase, new microcontrollers must be manufactured, swapped out, and limited to upgrade and expand on their own.
    [20] The present invention has been made to solve the above-mentioned problems of the prior art, and consists of a programmable logic device (PLD) or a field programmable gate array (FPGA) instead of a controller and a controller for applying a control signal for controlling a plurality of devices. The goal is to provide a device control system using SBEM that can simplify hardware configuration and extend control functions with ease.
    [1] 1 is a block diagram illustrating a device control system according to the prior art.
    [2] 2 is a block diagram illustrating a device control system in accordance with the present invention.
    [3] 3 is a diagram illustrating signals transmitted from a CPU board to an external board according to the present invention.
    [4] Figure 4 is a block diagram showing the interior of the SBEMC unit according to the present invention.
    [5] 5 is a diagram illustrating serial data in which header bits are formatted in an SBEMC unit according to the present invention;
    [6] Figure 6 is a block diagram showing the interior of the SBEMD unit according to the present invention.
    [7] * Description of the symbols for the main parts of the drawings *
    [8] 30: CPU board 31: CPU section
    [9] 33: SBEMC part 35: SBEMD part
    [10] X 1 ..... X n : device chip
    [21] In order to achieve the above object, the device control system according to the present invention,
    [22] A CPU board including a CPU generating a plurality of parallel device control signals and an SBEMC unit converting the parallel device control signals generated from the CPU into a serial control signal;
    [23] A SBEMD unit electrically connected to the CPU board and receiving a serial control signal generated from the SBEMC unit to transmit a control signal to each device, and a plurality of devices to be controlled by the control signal from the SBEMD unit. It is characterized by consisting of an external board including a chip.
    [24] Here, the SBEMC unit converts the parallel control signal generated from the CPU into a serial control signal, a header encoder unit for address decoding each of the converted serial control signals, and the address decoded serial control signal to the external device. A transceiver unit for transmitting to a board, wherein the header encoder generates a header bit indicating a corresponding device chip in each of the converted serial control signals, and the SBEMD unit receives a serial control signal transmitted from the SBEMC unit And a header encoder for removing header bits from the receiver and the received serial control signal, and a plurality of transceivers for applying the serial control signal from which the header bits are removed to the corresponding device chips.
    [25] The serial control signal transmitted from the SBEMC unit of the CPU board to the SBEMD unit of the external board is transmitted together with a clock, a frame, and a data (control) signal.
    [26] According to the present invention, it is possible to omit a controller and a controller for applying a control signal in order to control device chips, and to arrange a module composed of a PLD and an FPGA to simplify the hardware configuration of the board, and to easily expand the control device chip. There is an advantage.
    [27] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [28] 2 is a block diagram illustrating a device control system according to the present invention.
    [29] As shown in FIG. 2, the device control system includes a CPU board 30 that generates a control signal for controlling respective electronic devices X 1 ... X n disposed on the external board 50. The external board 50 is connected to the CPU board 30. The CPU board 30 is a SBEMC (Serial Bus Extend Module to CPU) for converting a parallel control signal generated by the CPU unit 31 and the parallel control signal generated by the CPU unit 31 into a serial control signal. Section 33).
    [30] The external board 50 receives a clock, a frame, and a control signal generated from the SBEMC unit 33 in the CPU board 30 to apply a control signal to a plurality of device chips (X 1 ... X n ). It consists of a SBEMD (Serial Bus Module to Device chip: SBEMD) unit 35.
    [31] The device control system having the above structure operates as follows.
    [32] First, the CPU unit 31 in the CPU board 30 generates a parallel control signal in order to control a plurality of devices X 1 ... X n disposed on the external board 50. The parallel control signal generated by the CPU unit 31 is applied to the SBEMC unit 33 and converted into a serial control signal. Then, the changed serial control (data) signal is applied to the SBEMD unit 35 disposed on the external board 50 together with the clock signal and the frame signal.
    [33] In addition, the SBEMD unit 50 controls the received serial signal controls each device chips (X 1 ... X n), a plurality of device chips (X 1 ... X n) by sending the.
    [34] The SBEMC unit 33 and the SBEMD unit 35 may be implemented as an FPGA (Field Programmable Gate Array) or PLD (Programmable Logic Device: PLD). The parallel control signal may be converted into a serial control signal. It is programmed to adjust the control signal, for example by converting and addressing each serial control signal by a header encoder.
    [35] 3 is a diagram illustrating signals transmitted from a CPU board to an external board according to the present invention.
    [36] As shown in FIG. 3, the SBEMC unit 33 of the CPU board 30 converts the parallel control signal generated by the CPU unit 31 into a serial control signal, and then converts the serial control signal (data signal) into data. The pin, clock pin, and frame are used to transmit the SBEMD unit 35 of the external board 50.
    [37] At the clock pin, a clock signal having a predetermined period is transmitted to the SBEMD unit for signal synchronization, and at the same time, a signal for distinguishing the start point and the end point of the effective portion of the serial control signal is displayed. A valid serial control signal exists between the start point and the end point of the frame signal and is transmitted to the SBEMD unit when the clock signal is synchronized.
    [38] Figure 4 is a block diagram showing the interior of the SBEMC unit according to the present invention.
    [39] As shown in FIG. 4, the parallel data signal generated by the CPU unit 31 in the CPU board 30 is applied to the serial converter 41 of the SBEMC unit 33 and converted into a serial data signal. The converted serial data signal is subjected to address decoding (adressing decording) in the header encoder unit 43, and then transmitted from the transceiver unit 45 to the SBEMD unit 45 through an interface.
    [40] 5 is a diagram illustrating serial data in which header bits are formatted in the SBEMC unit according to the present invention.
    [41] As shown in FIG. 5, after the serial data signal conversion described in FIG. 4 is converted, the serial data signal address-decoded by the header encoder 43 is shown.
    [42] After converting a plurality of device chip control signals generated in the CPU unit in series, header bits are encoded in each data signal to address which device each signal controls. The header bit is coded at the beginning of the serial data signals, so that when the serial data signal is applied from the SBEMD part of the external board, each signal can be distinguished which control device.
    [43] The number of bits of the header bits to be coded in the serial data signal is represented by an equation of N ≦ 2 n depending on the number of devices to be controlled. (N is the rewrite of the device chips, n is the number of header bits)
    [44] 6 is a block diagram showing the inside of the SBEMD unit according to the present invention.
    [45] As shown in FIG. 6, the serial data signal generated from the SBEMC unit 33 in the CPU board 30 is received by the receiving unit 51 of the SBEMD unit 35 in the external board 50. After being transmitted to the header encoder unit 52, the header encoder unit 52 of the SBEMC unit 35 removes the coded header bits from the serial data signal.
    [46] Each serial data signal from which the header bit is removed is applied to respective transceiver portions Y 1 ... Y n to control devices selected by the header bit. The transceiver units Y 1 ... Y n apply control signals generated from the CPU to device chips.
    [47] As described in detail above, the present invention has an effect of simplifying the hardware structure of the control system by using an SBEM programmed with a PLD or FPGA instead of a communication controller and a microcontroller used to control a plurality of device chips.
    [48] In addition, since the control system by the SBEM is easy to expand the number of device chips to control, there is an advantage that many device chips can be made without changing the components of the system.
    [49] The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] A CPU board including a CPU generating a plurality of parallel device control signals and an SBEMC unit converting the parallel device control signals generated from the CPU into a serial control signal;
    A SBEMD unit electrically connected to the CPU board and receiving a serial control signal generated from the SBEMC unit to transmit a control signal to each device, and a plurality of devices to be controlled by the control signal from the SBEMD unit. Device control system comprising an external board containing a chip.
    [2" claim-type="Currently amended] The method of claim 1,
    The SBEMC unit converts the parallel control signal generated from the CPU into a serial control signal, a header encoder unit for address decoding each of the converted serial control signals, and an address decoded serial control signal to the external board. Device control system comprising a transceiver for transmitting.
    [3" claim-type="Currently amended] The method of claim 2,
    And the header encoder generates a header bit indicating a corresponding device chip in each of the converted serial control signals.
    [4" claim-type="Currently amended] The method of claim 1,
    The SBEMD unit receives a serial control signal transmitted from the SBEMC unit, a header encoder unit for removing header bits from the received serial control signal, and a plurality of serial control signals for removing the header bits to each device chip. Device control system comprising a transceiver portion.
    [5" claim-type="Currently amended] The method of claim 1,
    And a serial control signal transmitted from the SBEMC unit of the CPU board to the SBEMD unit of the external board together with a clock, a frame, and a data signal.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-10-30|Application filed by 엘지전자 주식회사
    2001-10-30|Priority to KR1020010066956A
    2003-05-09|Publication of KR20030035079A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020010066956A|KR20030035079A|2001-10-30|2001-10-30|Device control system|
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